Fabrication of circuit packages
US4352449A · kind A · utility
26Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 26, 1979 |
| Grant date | Oct 5, 1982 |
| Priority date | — |
| Expiry date | Dec 26, 1999 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating circuit packages which employ macro-components (10) mounted on supporting substrates (20). In order to maintain sufficient clearance between the component and substrate and achieve high reliability bonds, massive solder preforms (16) are applied to contact pads on either the component or substrate. After contact pads of both carrier and substrate are brought into contact with the spheres, the bond is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.