Automatic power disconnect system for wafer scale integrated circuits
US4354217A · kind A · utility
17Cited by
3References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 7, 1980 |
| Grant date | Oct 12, 1982 |
| Priority date | — |
| Expiry date | Jul 7, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure relates to a wafer scale power interconnect system by which defective circuits on the wafer can be automatically disconnected from the power and ground lines supplied to each of the circuits. The disconnect device employs a gate between the power source and the circuit, which gate is controlled by a fuse that can be destroyed by an excessive current thereby opening the gate. The disconnect device may also be just such a fuse or a current limiter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.