Memory board automatically assigned its address range by its position
US4354258A · kind A · utility
22Cited by
2References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 11, 1980 |
| Grant date | Oct 12, 1982 |
| Priority date | — |
| Expiry date | Feb 11, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0676
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A subtractor circuit subtracts start address information supplied from address information to produce a logical address. An adder circuit adds the start address information to memory capacity information to form the start address of the succeeding memory board. When 0.ltoreq.output information from the subtraction circuit<memory capacity information, a memory board is selected. To obtain the selection signal, a comparing circuit is provided which compares the output information from the subtractor circuit with the memory capacity information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.