Transistor-transistor logic circuit
US4355246A · kind A · utility
7Cited by
5References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 8, 1978 |
| Grant date | Oct 19, 1982 |
| Priority date | — |
| Expiry date | Dec 8, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/001
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay element is introduced into a transistor-transistor logic circuit having a totem-pole-connected inverter transistor and an off-buffer transistor, in order to ensure a safe and correct operation even in the case where the transistor-transistor logic circuit is used as an element of multiple-connected transistor-transistor logic circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.