Semiconductor memory device
US4355375A · kind A · utility
25Cited by
2References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 27, 1981 |
| Grant date | Oct 19, 1982 |
| Priority date | — |
| Expiry date | Jul 27, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0425
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a plurality of floating gate transistors each of which comprises a semiconductor substrate, a first and second impurity doped region, channel region formed between the first and second impurity doped regions, a floating gate electrode formed on the channel region and separated into a plurality of portions at an intermediate portion of the channel region, and, a control gate formed on the floating gate and on the intermediate portion of the channel region. Part of the control gate is formed between the separated floating gate electrode portions and faces the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.