Apparatus and method of error detection and/or correction in a data set
US4355391A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 1980 |
| Grant date | Oct 19, 1982 |
| Priority date | — |
| Expiry date | Mar 31, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Matrix multiplication is used to generate error detection and/or correction binary code bits from a binary input word. A matrix made up of columns and rows of bits set to binary "1"s and "0"s in a pattern conforming to the mathematical expression of a predetermined error detection and/or correction code algorithm is set into a read only memory. The input binary word is 512 bits (64 bytes), one matrix being provided for each of the bytes. The first byte of the 512 bit word is multiplied by its respective matrix providing a ten bit binary code word. Simple odd parity is computed on the first byte and the odd parity bit is appended to the binary code word, which are stored in an accumulator. The next byte is multiplied by its respective matrix to provide another ten bit binary code word, and a simple parity bit is also generated. The second code word and parity bit combination is exclusively ORed in the accumulator with the first binary code word and first parity bit, thereby accumulating the correction and/or detection code. This procedure is continued until all 64 bytes have been handled. The 64 bytes and accompanying eleven error correction and/or detection bits are stored. When re…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.