Burst-error correcting system
US4355392A · kind A · utility
9Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1980 |
| Grant date | Oct 19, 1982 |
| Priority date | — |
| Expiry date | Dec 19, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1809
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a digital signal transmission system, a predetermined number of words of digital information signals are added bit by bit in a modulo 2 adder to produce a first parity signal. The information signals and the first parity signal are delayed so as to have different delay times to each other, and the signals thus delayed are again added bit by bit in a modulo-2 adder to produce a second parity signal. The predetermined number of words of information signals and first and second parity signals are serially transmitted through a transmission line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.