Method for fabricating a semiconductor read only memory
US4356042A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 1980 |
| Grant date | Oct 26, 1982 |
| Priority date | — |
| Expiry date | Nov 7, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/383
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process is disclosed for manufacturing a read only memory in which the specified bit pattern is fabricated into the memory at a late stage in the manufacturing cycle. Before the bit pattern is implanted into a ROM memory cell device (10), the cell is fabricated such that a substrate (12) has source (38) and drain (40) regions therein. A gate oxide (28) is positioned above the channel region of the device (10). A poly gate (30) is positioned immediately above the gate oxide (28) and below an oxide insulating layer (42). A further layer (45) of silicon dioxide is fabricated above the insulating layer (42). Metal contacts (48, 50) are fabricated to be in contact with the source region (38) and drain region (40) of device (10). A masking oxide (56) is deposited over the entire surface of the device (10). To incorporate the desired bit pattern a selected cell is ion-implanted to raise the voltage threshold of the cell. After masking with the customer pattern the insulating layer (45) is completely etched through and the insulating layer (42) is partially etched through above the poly gate (30a). An ion stream (60) is projected into the device (10) with sufficient energy to force the i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.