MOS Integrated circuit structure for discretionary interconnection
US4356504A · kind A · utility
15Cited by
4References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 28, 1980 |
| Grant date | Oct 26, 1982 |
| Priority date | — |
| Expiry date | Mar 28, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A flexible, symmetrical, MOS integrated circuit structure and layout employing a unit cell approach for customized wiring. Special features include multiple contacts on individual source/drain elements, rectilinear interconnections in the X- and Y- directions, and interconnection underpasses integral with the source and drain regions of the individual devices. The structure is especially applicable to complementary MOS integrated circuits of large complexity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.