Annealing of ion-implanted GaAs and InP semiconductors
US4357180A · kind A · utility
21Cited by
10References
8Claims
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Assignee
Inventor
Key dates
| Filing date | Jan 26, 1981 |
| Grant date | Nov 2, 1982 |
| Priority date | — |
| Expiry date | Jan 26, 2001 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/084
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of annealing both N and P-type ion-implanted GaAs and InP semiconductors by using a close-contact capping technique. A flat polished ion-implanted surface on a gallium arsenide (GaAs) or indium phosphide (InP) semiconductor is placed in face-to-face contact with a non-reactive flat surface such as Si.sub.3 N.sub.4, SiO.sub.2, AlN, or identical semiconductor material, and annealed at selected elevated temperatures and time dependent upon ion concentration. The annealed semiconductor material, usually in the form of a wafer, is allowed to cool to room temperature for further processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.