Multislope converter and conversion technique
US4357600A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 1980 |
| Grant date | Nov 2, 1982 |
| Priority date | — |
| Expiry date | Nov 10, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/52
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multislope A/D converter is presented which employs a multislope integration technique enabling the use of a single comparator to detect polarity changes in the integrator output voltage. The A/D converter integrates a test signal during a run-up interval and integrates a discharging signal during the run-up interval as well as during a pre-run-down interval and a run-down interval subsequent to the run-up interval. The magnitude and polarity of the discharging signal are regulated in accordance with a switching scheme that converts circuit element mismatch error into offset measurement errors which can be eliminated by subtraction. The discharging current during the pre-run-down interval ensures that the slope of the integrator output voltage at the final polarity change is independent of test signal polarity thereby avoiding a comparator hysteresis error. A decade-run-down technique is employed during the run-down interval enabling the digital conversion to be implemented on a decade counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.