Programmable sequential logic array mechanism
US4357678A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 26, 1979 |
| Grant date | Nov 2, 1982 |
| Priority date | — |
| Expiry date | Dec 26, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1772
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable sequential logic array mechanism is provided for performing logical operations and solving logical equations. The mechanism includes a search array subsystem for receiving a plurality of binary input signals. The search array subsystem includes an addressable storage array for supplying input control words for testing for different input signal conditions. The sequential logic array mechanism also includes a read array subsystem for producing a plurality of binary output signals. This read array subsystem includes an addressable storage array for supplying output signal control words. The results of the tests performed by the search array subsystem are used to select which ones of the output signal control words are allowed to establish or change the read array output signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.