Method and apparatus for testing and verifying the operation of error control apparatus within a memory
US4359771A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 1980 |
| Grant date | Nov 16, 1982 |
| Priority date | — |
| Expiry date | Jul 25, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Soft error rewrite control apparatus is included within a memory system for rendering the semiconductor memory modules less susceptible to single bit errors produced by alpha particles and other system disturbances. During a number of successive memory cycles occurring at a predetermined rate, the soft error rewrite control apparatus enables the read out of information stored within each module location, the correction of any single bit errors contained therein and the rewriting of the corrected information back into such location. Diagnostic apparatus is further included which is connected to place the memory system in a state for testing and verifying the operation of the soft error control apparatus. Also, the diagnostic apparatus is connected to condition the soft error control apparatus for operating in a high speed mode enabling the read out correction and rewriting of each location to take place within a minimum amount of time. By monitoring the status of the information being corrected, the diagnostic apparatus is able to signal whether or not the soft error control apparatus is operating properly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.