Address and data interface unit
US4360891A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1980 |
| Grant date | Nov 23, 1982 |
| Priority date | — |
| Expiry date | Apr 14, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A large scale integrated circuit is designed to handle bus-to-bus data and address transfers, manipulation, and temporary storage. A key feature of the device is that it generates error correcting code parity bits on a byte wide basis so that ECC check bits for a multi-byte word can be generated externally with a minimum of hardware, and includes circuitry responsive to an error syndrome for correcting a single error within a byte. Data manipulation capabilities include standard logical operations, single bit shift operations, binary 2's complement arithmetic addition and subtraction, and decimal addition and subtraction. In addition, an input data byte on any bus can be passed unaltered or inverted to any other bus. The device is capable of receiving operands from one or two of three bidirectional data buses, performing a desired arithmetic or logical operation on the operand or operands, and returning the result to any one of the bidirectional buses including one which may have supplied one of the operands. An instruction is decoded at the leading edge of a clock pulse, and executed during the clock pulse. The result is entered into a result register on the trailing edge of the c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.