Clocking system for a self-refreshed dynamic memory
US4360903A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 1980 |
| Grant date | Nov 23, 1982 |
| Priority date | — |
| Expiry date | Sep 10, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clocking system for a self-refreshed dynamic memory (10) for reading data stored in a memory cell (30) and including clocking circuitry (68) includes detecting changes in an address signal (60). The method further includes generating a memory refresh signal (64, 66) in response to detecting changes in the address signal (60). The memory refresh signal (66) is applied to the semiconductor memory circuit (30) for refreshing data stored in the memory cells of the semiconductor memory circuit (30). After the application of the memory refresh signal (66) to the semiconductor memory circuit (30) the address signal (16) is applied to the semiconductor memory circuit (30) for accessing the addressed memory cell to thereby read the data stored therein. The clocking circuitry (68) is reset and precharged during the application of the refresh signal (66) to the semiconductor memory circuit (30).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.