Parity fault locating means
US4360917A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1980 |
| Grant date | Nov 23, 1982 |
| Priority date | — |
| Expiry date | Oct 14, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and method are provided for isolating errors in a logic system employing memory and having a data transmission bus structure. A memory readout error is detected in a multibit word having a parity bit added thereto by parity checking means. A readout error, commonly referred to as a "soft read error", is an erroneous output from a memory device that is transient in nature in that the soft read error is corrected when the memory device is refreshed or reread. It is contemplated that such a readout error may take place when a multibit word is outputted from a refresh type random access memory such as a dynamic random access memory (RAM) or a write after read core memory. In response to the detection of an error condition in the memory by the parity bit error detector, the memory is read again in order to obtain a second output. If the second output provided by the memory does not contain a parity error, the prior error is considered to be a soft read error and the second data word is forwarded to a utilization device such as a CPU. If the second output from the memory also contains a parity error, such an error is considered to be a "hard read error" and the data is not util…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.