Microcomputer with logic for selectively disabling serial communications
US4361876A · kind A · utility
14Cited by
17References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 5, 1978 |
| Grant date | Nov 30, 1982 |
| Priority date | — |
| Expiry date | Sep 5, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/161
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A single-chip microcomputer includes a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), and four I/O ports (11-14). The serial I/O communication logic includes a control and status register (46), one bit (WU) of which may be utilized, when the microcomputer is connected in a distributed processing system having a shared serial communication line, to indicate that the CPU wishes to ignore a message not of interest to it. When the serial communication line again becomes free, the WU control bit is reset, enabling the CPU to intercept a new message of interest.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.