Circuit arrangement for clock pulse recovery at the receiving end of digital clock-controlled data transmission systems
US4361897A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 14, 1980 |
| Grant date | Nov 30, 1982 |
| Priority date | — |
| Expiry date | Oct 14, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement for clock pulse recovery on the receiving side of a digital clock-controlled data system is particularly characterized in that in the receiver a branch circuit is connected to the input side in parallel with a digital converter for converting the digital data signal, the branch circuit comprising an EXCLUSIVE or gate having two inputs and a delay element in the feed to one input of a digital counter which is connected to the output of the EXCLUSIVE OR gate and actuated by a quartz-stabilized oscillator having a frequency of multiple of the desired timing frequency and whose output is connected to the digital converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.