Method of fabricating high-conductivity silicide-on-polysilicon structures for MOS devices
US4362597A · kind A · utility
39Cited by
2References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1981 |
| Grant date | Dec 7, 1982 |
| Priority date | — |
| Expiry date | Jan 19, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
It is known to deposit a refractory metal silicide on a polysilicon gate layer to form a low-resistivity composite structure. For VLSI MOS devices, very-high-resolution patterning of the composite structure is required. In accordance with this invention, a silicide pattern is formed on polysilicon by a lift-off technique. In turn, the patterned silicide is utilized as a mask for anisotropic etching of the underlying polysilicon. High-conductivity composite silicide-on-polysilicon gate structures for VLSI MOS devices are thereby achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.