Clock pulse tolerance verification circuit
US4362957A · kind A · utility
16Cited by
4References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 29, 1980 |
| Grant date | Dec 7, 1982 |
| Priority date | — |
| Expiry date | Dec 29, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/26
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement for comparing a clock pulse train against a standard pulse train. The circuit includes an exclusive OR gate to which are inputted the pulse train to be tested, and a latch at the output of the gate, operated only upon a mismatch of the two pulse trains. Provision is also made to prevent operation of the latch within certain adjustable tolerance parameters as to pulse width and position of the pulse train.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.