Clock recovery apparatus for phase shift keyed encoded data
US4363002A · kind A · utility
42Cited by
3References
10Claims
0Family size
Inventor
Key dates
| Filing date | Nov 13, 1980 |
| Grant date | Dec 7, 1982 |
| Priority date | — |
| Expiry date | Nov 13, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4904
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A pseudo clock generator produces pulses synchronous with, and having a period equal to one-half of the clock signal within a phase shift keyed encoded data stream. A phase lock circuit, having a stable period equal to that of the data clock signal tends to lock to the pseudo clock signal. Logic detects the condition of the phase lock signal being in phase lock with said data clock signal and in response thereto, masking circuitry prevents the pseudo clock generator from responding to input data transitions which occur outside of a predetermined masking window.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.