Hit/miss logic for a cache memory
US4363095A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1980 |
| Grant date | Dec 7, 1982 |
| Priority date | — |
| Expiry date | Dec 31, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system a cache memory comprises level one and level two even and odd data stores and level one and level two even and odd directory stores. The directory stores include a plurality of storage locations for storing the most significant bits of the address numbers associated with the data words stored in the level one and level two even and odd data stores. The level one and level two even and odd directory stores are addressed by the least significant bits of the address numbers. Comparator circuits compare the high order bits of an address number supplied in a memory request to the high order bits stored in the level one even and odd directory stores at storage locations identified by both the low order bits of the address supplied in the memory request and the low order address bits incremented by one. A hit detector circuit determines whether one, both, or none of the requested words are stored in the cache memory by analyzing the outputs of the comparators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.