Speech detector circuit for a TASI system
US4365112A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1980 |
| Grant date | Dec 21, 1982 |
| Priority date | — |
| Expiry date | Mar 17, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/175
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Disclosed is a centralized circuit for determining whether input signals from a plurality of channels are speech which includes memory means in which digital amplitude samples from each of the input channels are stored in real time. A control means then periodically retrieves the samples from the memory in a time faster than real time and produces a series of time compressed input signals which are compared with a variable threshold derived from a stored level for each channel. Moreover, means are disclosed for setting a new threshold whenever the time compressed input signals differs from the old level for a predetermined time, the new level thereafter being stored in place of the previously stored old level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.