Two speed recirculating memory system using partially good components
US4365318A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1980 |
| Grant date | Dec 21, 1982 |
| Priority date | — |
| Expiry date | Sep 15, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/86
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CCD recirculating memory system is disclosed in which "partially good" CCD memory chips and "all good" memory chips are mounted on memory cards. The defective portions of the partially good chips are in the same chip octants on the same card. The cards are addressed by address permutation means which causes the defective portions to appear to have the same predetermined address to the operating system. The addressed CCD row on the partially good chips are clocked at a fast rate while the unaddressed rows are clocked at a slow rate. All of the rows of the "all good" chips are clocked at a fast rate when a defective portion of the partially good chips is being addressed and are otherwise clocked at a slow rate. A select signal is generated whenever the predetermined address is invoked and causes the substitution of an all good chip for the addressed partially good chip. The select signal also selectively prevents another memory access from occurring until resynchronization is achieved between the last accessed chip and the unaccessed chips. The arrangement minimizes waiting time between successive memory accesses in a two speed partially good recirculating array without the need to…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.