Level conversion circuit
US4366397A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jun 9, 1980 |
| Grant date | Dec 28, 1982 |
| Priority date | — |
| Expiry date | Jun 9, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The collectors of differential pair transistors having their emitters connected to each other are connected to a positive power source voltage via respective load resistors. The emitters are connected to a negative power source voltage via a current source transistor. The base bias voltage of the current source transistor is supplied from a bias circuit operating on the difference voltage between the positive power source voltage and the negative power source voltage. When the positive power source voltage drops, the base bias voltage of the current source transistor drops in response thereto. Hence, the value of a current flowing through the current source transistor decreases. Due to this decrease of the current, the voltage drop of the load resistors decreases, thereby off-setting a low level potential of the collector output signals of the differential pair transistors. Thus, the differential pair transistors are prevented from being driven into saturation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.