Memory controller with queue control apparatus
US4366538A · kind A · utility
77Cited by
4References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1980 |
| Grant date | Dec 28, 1982 |
| Priority date | — |
| Expiry date | Oct 31, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller couples to a bus and controls a number of memory module units or memory modules. The controller includes a number of queue circuits for processing a variety of different types of memory requests received from a number of command generating units coupled to the bus requiring the controller to operate in a corresponding number of different modes. The controller includes queue timing and control apparatus which couples to the modules and to the queue circuits for minimizing conflicts between the types of requests and the internal operations required to be performed by the controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.