Memory controller with burst mode capability
US4366539A · kind A · utility
34Cited by
6References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1980 |
| Grant date | Dec 28, 1982 |
| Priority date | — |
| Expiry date | Oct 31, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller coupled to a number of memory module units and includes a number of control circuits. The control circuits include address counter circuits which are loaded with a portion of the address of each predetermined type of command or memory request from a requesting device. This command when decoded causes the controller to read out from the memory module units a predetermined number of word pairs starting with the location specified by the stored address portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.