Power down detector
US4366560A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 1980 |
| Grant date | Dec 28, 1982 |
| Priority date | — |
| Expiry date | Sep 22, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/143
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for detecting power supply variations in which a first and second transistor are connected in a cross-coupled mode. A load device is connected to each transistor and to a source of power. The loads are unbalanced such that upon application of power to the circuit a first state is always assumed. The cell is forced to its second state. A charge transfer device is connected between first and second nodes formed at the connection between the first transistor and its load and the second transistor and its load. Upon reduction of power supply voltage below that of the active node, a charge transfer takes place which allows the cell to return to its initial state. Detection of the initial state indicates loss or reduction of power has occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.