Reset signal generator
US4367423A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 6, 1981 |
| Grant date | Jan 4, 1983 |
| Priority date | — |
| Expiry date | Jan 6, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2017/226
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reset generator circuit including a power monitor subcircuit which provides first and second logic level signals which specify the power supply as being above or below a preselected threshold level. A logic circuit comprising a series of interconnected NAND gates responds to the output signals generated by the power monitor subcircuit and to a signal from a capacitor charge monitor circuit. The capacitor charge monitor circuit develops logic signals which reflect the magnitude of the voltage across a capacitor which is part of a timing circuit. The control signal output from the logic circuit drives one input to a reset control gate and also controls the charge on the capacitor. The other input to the reset gate is also driven by the charge monitor circuit. The reset gate operates a switching element which provides the proper reset signal adapted for coupling to a microprocessor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.