Display refresh memory with variable line start addressing
US4368466A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 20, 1980 |
| Grant date | Jan 11, 1983 |
| Priority date | — |
| Expiry date | Nov 20, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/222
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display refresh system wherein a RAM refresh buffer is tightly packed. Line start addresses in the buffer are determined by the line length such as eighty characters. With each of the lines in the refresh buffer being normally a binary number such as 128 characters in length the line start addresses are such that they do not coincide with the beginning of each line in the buffer. To assure packing they are interspersed each 80 positions sequentially within the buffer. A processor loads the address of each line start character into the pointer area of the refresh buffer. A line counter is used which counts the lines being displayed on the display. The RAM refresh buffer which contains the line start addresses and character data is first addressed by the line counter output to provide the line address. Since the refresh buffer is used as the line pointer register the output bus for pointer data and character data is common. Once the address of the first character in a line is read from the pointer area in the refresh buffer it is loaded into the refresh buffer address counter which then controls the sequential reading of characters in that line from the refresh buffer onto the data…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.