Silicon barrier Josephson junction configuration
US4368479A · kind A · utility
4Cited by
2References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 29, 1980 |
| Grant date | Jan 11, 1983 |
| Priority date | — |
| Expiry date | Oct 29, 2000 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S505/874
Abstract
A planar, silicon barrier, Josephson junction and method of forming the junction which does not require expensive high-resolution, lithography techniques such as electron beam or x-ray. The method includes an etching mask-etch process which forms the basic structure configuration using a (110)-cut silicon wafer. Subsequent to the etching process the mask is removed and a superconducting film is deposited on the previously formed silicon surface to produce a single crystal silicon barrier with good electrical properties.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.