Multi-processor system
US4368514A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 1980 |
| Grant date | Jan 11, 1983 |
| Priority date | — |
| Expiry date | Apr 25, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed a multi-processor system having a master processor and a plurality of slaves. Each processor is provided with its own memory. Although each slave processor can access only its respective memory, the master processor can access either its own memory or any one of the slave memories. Maximum throughput (efficiency) is achieved by suspending operation of a single slave processor for only a single memory cycle, i.e., the time required for the master processor to access the respective slave memory. Each processor/memory is on a single card, with all of the cards being connected to a common bus. The cards are virtually identical, and master/slave distinctions are determined by a single slot bit on each card. A unique addressing scheme is implemented for access from the master to a selected slave.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.