Bank switchable memory system
US4368515A · kind A · utility
83Cited by
9References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 7, 1981 |
| Grant date | Jan 11, 1983 |
| Priority date | — |
| Expiry date | May 7, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decoding circuit is coupled to the signal lines that communicate address signals to a memory unit. When a predetermined address is communicated, the decoding circuit produces a supplemental signal that is coupled to the memory unit and used to select one of a plurality of groups of memory locations. The communicated address signals specify the memory location of the selected group to be accessed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.