Soft error rewrite control system
US4369510A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 1980 |
| Grant date | Jan 18, 1983 |
| Priority date | — |
| Expiry date | Jul 25, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/106
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Refresh and initialize counter circuits included within a dynamic memory system are supplemented with additional counter control circuits for synchronizing them from the same timing source which drives the refresh and initialize counter circuits. The counter control circuits count in accordance with modulus one less than a maximum count so as to generate a sequence of counts over a corresponding number of cycles of operation for selection of row and column addresses which enable the information stored in each location of the memory system to be read out, corrected for single bit errors and rewritten back thereby rendering the system less susceptible to soft errors such as those produced by alpha particles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.