Self-clocking data transmission system
US4369516A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 15, 1980 |
| Grant date | Jan 18, 1983 |
| Priority date | — |
| Expiry date | Sep 15, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4904
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data transmission system is described where data signals are bidirectionally transmitted between a data transmitter and a plurality of data receivers in a self-clocking bit streams carried on true data and complement data signal lines and a non-return-to-zero (NRZ) bit streams on a return data signal line. According to an inventive data transmission scheme, data signals are transmitted by the data transmitter by utilizing the four possible two-bit binary states of the true data and complement data signal lines. Of the four two-bit binary states, a word state is provided before and after the data signal and a one state or zero state followed by a bit state is provided for each bit of the data signal. The data receivers detect the bit state to recover a bit clock signal and detect the one state and zero state to recover an NRZ data signal. In response to the bit clock signal, the NRZ data signal is serially shifted into a register while a previously parallel loaded return data signal is shifted out of the register and applied to the return data signal line. The inventive data transmission scheme is self-clocking and highly immune to speed and timing variations in the transmission. …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.