Computer emulator with three segment microcode memory and two separate microcontrollers for operand derivation and execution phases
US4370709A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 1, 1980 |
| Grant date | Jan 25, 1983 |
| Priority date | — |
| Expiry date | Aug 1, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/226
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microcoded central processing unit (CPU) is used to emulate the macroinstructions of a target computer. Each macroinstruction emulated is divided into two phases, an operand derivation or classification phase and an instruction execution phase. A microcontroller is provided to control each of the two separate phases. The two microcontrollers operate in parallel and simultaneously in performing their respective operations. The two microcontrollers are synchronized together so that when one microcontroller needs access to CPU resources that are currently under control of the opposite controller, the requesting microcontroller is put to sleep until the needed resource comes available before it continues its operations. Microcode is minimized by sectionalizing the micromemory such that certain microcode can be shared by both microcontrollers where common microcode is needed to emulate different macroinstructions. A three section micromemory is provided with the right section normally associated with the operand derivation, the left section associated with the instruction execution, and the middle micromemory available to either microcontroller. Either microcontroller may specify the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.