Branch predictor using random access memory
US4370711A · kind A · utility
58Cited by
2References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 21, 1980 |
| Grant date | Jan 25, 1983 |
| Priority date | — |
| Expiry date | Oct 21, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is provided for predicting in advance the result of a conditional branch instruction in a computer system. The system includes a hash mechanism, a random access memory, an address buffer, a branch outcome result receiving means and a counter buffer. The hash mechanism and memory use the input branch instruction address to produce a count which in effect is a way of weighting recent branch history to predict the branch decision. The counts are stored in the random access memory (RAM). The random access memory is addressed by the hashed branch instruction address to produce the system result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.