Memory controller with address independent burst mode capability
US4370712A · kind A · utility
21Cited by
5References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1980 |
| Grant date | Jan 25, 1983 |
| Priority date | — |
| Expiry date | Oct 31, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller couples to a number of memory modules and includes a number of control circuits. The control circuits include address counter circuits which are loaded with a portion of the address of each predetermined type of command from a requesting device. This command when decoded causes the controller to read out from the memory modules a predetermined number of words starting with any word boundary at the location specified by the stored address portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.