Memory address selector
US4370746A · kind A · utility
24Cited by
10References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 24, 1980 |
| Grant date | Jan 25, 1983 |
| Priority date | — |
| Expiry date | Dec 24, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3193
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A testing apparatus, having an address generator for providing address signals to a test device and to a reference device, is provided with a programmable mask for passing only selected least significant X and Y address bits to the reference device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.