Load distribution among parallel DC-DC converters
US4371919A · kind A · utility
24Cited by
6References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1981 |
| Grant date | Feb 1, 1983 |
| Priority date | — |
| Expiry date | Apr 29, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/285
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A control circuit (36) on the primary side of a converter senses the output voltage and is useful for modulating the drive pulse width of a switching transistor (30). An averaging circuit (78) averages the drive pulse and compares this average with an average of the drive pulses for all switching transistors in a system of parallel converters to produce an error signal. In response to the error signal, the drive pulse width is varied so that the load current is distributed evenly among the parallel converters to improve the system efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.