Input/output information indication system
US4371926A · kind A · utility
8Cited by
9References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 1980 |
| Grant date | Feb 1, 1983 |
| Priority date | — |
| Expiry date | Mar 6, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In data processing apparatus in which address and data are transferred by means of DMA through an address bus and a data bus, a coincidence circuit determines whether the address on the address bus coincides with an address designated by an address designation device, a latch circuit latches the data on the data bus when the coincidence is detected and stores the latched data, and an indicating device indicates the data stored in the latch circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.