Fast updating peak detector circuit
US4373141A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 22, 1981 |
| Grant date | Feb 8, 1983 |
| Priority date | — |
| Expiry date | Jan 22, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A peak detector circuit (10) is disclosed wherein an input signal is full-wave rectified by a circuit (14) and the rectified signal is provided simultaneously to peak detect, hold and dump circuits (18), (20). Each of the peak detect, hold and dump circuits is discharged at the start of periodic intervals with a phase offset between the intervals for the two circuits. The peak signals are discharged at essentially the start of the interval followed by rapid charging of the peak signal to the peak amplitude of the rectified input signal. The later portions of each of the intervals of the peak signals produced by the peak detect, hold and dump circuits (18) and (20) are transmitted alternately through a multiplexer circuit (24). The resulting output signal is transmitted through a high impedance buffer amplifier (30) to an output terminal (32) of peak detector circuit (10). The timing of the operation of multiplexer (24) serves to remove the discharge and charge transitions of the peak signals from the peak detected output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.