Fail safe digital timer
US4373201A · kind A · utility
8Cited by
6References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 28, 1980 |
| Grant date | Feb 8, 1983 |
| Priority date | — |
| Expiry date | Nov 28, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1608
- WIPO fieldThermal processes and apparatus
- WIPO sectorMechanical engineering
Abstract
A fail safe digital timer is provided by having a pair of similar counters counting the output of a single clock means. The clock means provides clock pulses and complimentary clock pulses to the two counters and the outputs of the counters are compared. If the two counters are properly operating the comparison will provide a continuous stream of pulses at a frequency equal to the frequency of the clock means for the timer. The failure of any of the components in the system cause the output of the comparator means to either become a constant logic 1 or a constant logic 0.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.