Method for manufacturing a semiconductor structure having reduced lateral spacing between buried regions
US4373252A · kind A · utility
23Cited by
11References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 17, 1981 |
| Grant date | Feb 15, 1983 |
| Priority date | — |
| Expiry date | Feb 17, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76216
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The lateral spacing between buried regions separated by oxide-isolation regions in a semiconductor structure is reduced to as little as one micron by performing a deep implantation of ions of the conductivity type opposite to that of the buried regions generally into portions of the substrate below the sites where the oxide-isolation regions are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.