Clock failure monitor circuit employing counter pair to indicate clock failure within two pulses
US4374361A · kind A · utility
19Cited by
5References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 29, 1980 |
| Grant date | Feb 15, 1983 |
| Priority date | — |
| Expiry date | Dec 29, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R29/033
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A monitor circuit, for use in a switching system which detects pulse failures through use of a pair of timing counters. A flip-flop enables and clears such counter alternately in response to detection of the monitored pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.