High contrast alignment marker for integrated circuit fabrication
US4374915A · kind A · utility
23Cited by
6References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1981 |
| Grant date | Feb 22, 1983 |
| Priority date | — |
| Expiry date | Jul 30, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F9/00
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A wafer marker is described for aligning masks with the wafer. The marker comprises a depression in the wafer which is defined by sloped sides and a pitted bottom. The sloped sides and pitted bottom do not directly reflect light as does the surface of the surrounding silicon and thus the marker appears as a darker region. The bottom of the depression is pitted by exposing the anode during a silicon plasma etching step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.