Virtual memory addressing device
US4376297A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1980 |
| Grant date | Mar 8, 1983 |
| Priority date | — |
| Expiry date | Jun 2, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic address translation unit for converting virtual or "logical" address values into real or "physical" address values. A translation Lookaside Buffer (TLB) stores physical addresses corresponding to a limited number of previously translated logical addresses. The available space in the TLB is divided into partitions, each of which stores address translation data for a particular user process. The TLB partition in current use is identified by the value stored in a user partition counter, which is also used to verify that certain process control information (stored in a stack memory location) associated with the partition matches the process control information for that user process which is currently in control of the central processing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.