Associative memory system
US4376974A · kind A · utility
13Cited by
12References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1980 |
| Grant date | Mar 15, 1983 |
| Priority date | — |
| Expiry date | Mar 31, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/90339
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An associative memory system including a plurality of associative data controllers (ADCs) which operate in parallel upon a mass storage including a storage array for each ADC. A primitive function processor (PFP) couples the ADCs to a control unit which provides user access to the system. Hardware instructions are issued by the PFP to the ADCs to enable them to operate in parallel. The ADCs have circuits for performing simultaneous read/write operations with their related storage arrays, and for performing tagging operations, minimum/maximum operations, and logical operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.