Synchronization loss tolerant cyclic error checking method and apparatus
US4377863A · kind A · utility
11Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 8, 1980 |
| Grant date | Mar 22, 1983 |
| Priority date | — |
| Expiry date | Sep 8, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/18
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system wherein a binary data message is protected by cyclic check codes, synchronization loss tolerance is incorporated by performing a binary transformation after encoding the message but prior to transmitting it or writing it to storage and by performing an inverse binary transformation upon receiving it or reading it from storage but prior to error checking. In one embodiment the transformation involves complementing a plurality of bits. In an alternate embodiment the transformation involves reversing the sequence of a plurality of contiguous bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.