Method for manufacturing an I.sup.2 L semiconductor device
US4377903A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 1981 |
| Grant date | Mar 29, 1983 |
| Priority date | — |
| Expiry date | Feb 18, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An oxide layer is partially formed on an n-type region surrounded by a field oxide region. A base region of a switching transistor is formed in the n-type region using as a mask the oxide layer. Arsenic-doped polysilicon layers are selectively formed simultaneously on the surfaces of the oxide layer and the base region. Using the polysilicon layers as a mask, the emitter and collector regions of an injector transistor and the external base region of a switching transistor are formed in the n-type region and the base region respectively. Arsenic doped into the polysilicon layers is diffused into the base region, so that the collector regions of the switching transistor are self-aligned with the polysilicon layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.